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Volume Number:1
Issue Number:11
Column Tag:The Electrical Mac

Macintosh PAL Technology

By Jeff Mitchell, President, Digital Solutions, MacTutor Contributing Editor


Among its other achievements, the Macintosh has stirred considerable interest and spawned many rumors on the subject of PALs®. Most computer enthusiasts are familiar with hardware terms like microprocessor, TTL, and UART. Programmable logic, of which PALs are just one of several types, is a relatively recent phenomenon, and hadn't received much attention from the general press until the Mac arrived with its logic board full of it. It seemed as if everyone was convinced Apple had been able to package some black magic in a mysterious device called a PAL.

My aim this month is to dispel the mystery surrounding PALs. I'll describe the various types of programmable logic devices (PLD), detail their various internal architectures, and explain what it is they actually do. I'll present an application which demonstrates the value of these devices, and finally I'll describe the functions the HAL devices in the Macintosh perform.


A PAL is one of several types of field programmable logic, of which the PROM is the best known. Field programmable means the user can program his logic into the device himself, rather than the logic being part of the semiconductor manufacturing process as with mask ROMs.

Current digital design practice consists mostly of tying several LSI devices together with some 'glue logic', consisting of some number of SSI and MSI TTL devices which serve to generate control signals for the LSI. Although necessary, this glue logic takes up a large amount of space due to its low level of integration. This is where programmable logic devices come in. They serve as replacements for random logic and provide much more functionality than SSI TTL devices in a similar size package. Signetics claims that the replacement of 15-20 I.C.'s with one 82S100 FPLA is not unusual. My experience is that replacement of 2-5 I.C.'s is a more realistic figure.

The reason that programmable logic can be used to replace random glue logic is that any logic equation can be reduced to a sum of products; that is, groups of AND terms connected by OR terms. Not surprisingly, programmable logic devices consist of an array of AND gates feeding an OR gate.


There are many advantages to using programmable logic rather than discrete TTL devices. There is the PC board real estate that is saved when several devices are replaced by one, along with an accompanying power savings, although this can depend on how many devices were replaced. All but the newest PLDs are fabricated using bipolar technology, which consumes large amounts of power. On the other hand, bipolar technology is fast, and there is a lot less propagation delay through a single PLD than through several TTL devices, allowing the designer to increase circuit performance as well as save space.

The design stage of product development is where PLDs are most valuable. Changing the circuit logic is as simple as reprogramming a single chip with a different logic equation. This saves countless hours of rewiring, and lets the designer experiment with circuits he might otherwise not try.

PLDs play a role in manufacturing, too. A single device may replace several different types of TTL logic, reducing inventory and purchasing requirements. Bugs found after the product has been shipped may be correctable by changing the PLD, instead of costly cut-and-jumper rework to the PC board.

There's a down side to using programmable logic, though. These devices are significantly more expensive than jellybean TTL parts, on the order of several dollars as opposed to less than a dollar. But this is only the component price and does not include the savings from a smaller PC board, less assembly labor, less inventory, and perhaps a smaller power supply. There is also the option of turning a programmable device into a high-volume masked part, which is what Apple has done with the Macintosh.

PLDs are generally used where there is considerable random logic, or where space is at a premium, yet the production quantities cannot justify the expense involved in designing a fully custom device; i.e. a gate array or standard cell.


Bipolar proms were the first devices used to replace random logic, usually in address decoding applications. In 1975, Signetics Corporation developed the FPLA (Field Programmable Logic Array), which allowed a fully customizable implementation of sum-of-products equations. This was the first device aimed specifically at replacing random logic. Monolithic Memories, Inc. (MMI) soon followed with the PAL (Programmable Array Logic), which while similar to the FPLA in concept, differs in its internal implementation of the sum-of-products logic.

Both of these devices were based upon fuseable-link bipolar PROM technology, in which the device is programmed by injecting large currents into specific locations, vaporizing selected internal fuses. The remaining intact fuses determine what transfer equation will be implemented.

Since the introduction of PLDs, the technology has advanced, increasing the speed, programming yields, and reliability of the parts. The general architecture has not changed, although more complex devices have been introduced as the market matures and new applications appear.


PLDs have their own symbols and logic notation, which I'll introduce here, and then go on to describe the internal architecture of each of the three types of programmable logic, PROMs, PALs, and FPLAs.

An AND gate is normally portrayed as in Figure 1a. Figure 1b shows how this same gate is represented when implemented in programmable logic. The X's indicate an intact fuse. Figure 1c shows the device in (b) programmed, with input B removed from the equation. The lines still cross, but the missing X indicates that a fuse has been blown. Figure 1d is the same gate, but is not programmable. An intersection with a dot is hard-wired internally.

Internal to the device, logic states are always active high. The output of an AND gate is only high if all connected inputs are high, and the output of an OR gate is high as long as at least one of the connected inputs is high. All symbolic logic inversion takes place only at the input and output buffers. This can get quite confusing with PAL devices, most of which do not have programmable output polarity. This makes it necessary to apply DeMorgan's Law to your logic equation if you want to change its output polarity (Figure 2). Fortunately, this is taken care of for you if you are using one of the several logic compilers available, which I'll briefly describe later.

Figure 3 shows the logic representation of an input buffer. All signals are passed into the programmable array in both their normal and inverted states. This eliminates the need to have signals of the correct polarity available at the inputs to the device.


PROMs, PALs, and FPLAs differ in the way that they implement the standard sum-of-products equation. These differences affect their flexibility, speed, and potential applications.

PROMs were the original programmable logic devices, and as such are the least flexible. They are also the least complex and the least expensive. MMI is attempting to resurrect PROMs as legitimate replacements for random logic by providing support for them in their logic compiler and by renaming them Programmable Logic Elements (PLE). This ploy was obviously dreamed up by the marketing department. A rose by any other name . . .

The internal structure of a PROM consists of a fixed AND array followed by a programmable OR array. This is shown in Figure 4. The most common use for a PROM is as a computer program store, where the inputs are addresses and the outputs are data. They are also used as lookup tables, where the input would be a variable and the output is some function of that variable, for example output = SIN (input). PROMs are good for applications where every possible input combination has an associated output value, which is rarely the case with random logic.

The basic structure of a PAL, shown in figure 5, is very similar to that of a PROM. The difference is that now it is the OR array that is fixed and the AND array that is programmable. This architecture is much better suited to the replacement of random logic.

The ultimate in flexibility is the FPLA. As you can see from figure 6, in this device both the AND array and the OR array are programmable. This provides the designer the capability to implement any logic function, as long as there are enough terms available. This extra capability extracts a price in increased device complexity, which makes the part more expensive. The additional fuses also increase the propagation delay through the device, since there is a capacitance associated with each unblown fuse. This encourages designers who require speed to shy away from FPLAs, although if all the unused fuses are blown they are just as fast as PALs. Unfortunately, this is not reflected in the data sheets for FPLAs, so not everyone is aware of this.

The last type of programmable logic device is really not programmable at all. The HAL® (Hard Array Logic) is a custom PAL device. It is actually HALs that are inside the Macintosh, not PALs. If product volume warrants it, a semiconductor mask can be made from a PAL fuse map. Custom devices are then made from these masks. A HAL is to a PAL as a ROM is to a PROM. This is quite a boon to the designer, who can prototype using PALs, then use HALs for high volume production. This is unlike gate arrays, which cannot be tested in an actual circuit until the design is done, masks are made, and production parts come off the line.


Once it has been decided what logic functions a PLD is to perform, how is the device programmed? There are several methods, but only a couple of practical ones. Most PROM programmers will, with additional attachments, program PLDs also. These programmers generally accept fuse-map data, which tells it which fuses are to be blown. Not being computers, we would prefer to input the data as boolean equations.

MMI was the first to fill the need for a 'silicon compiler' when they made PALASM® (PAL assembler) available. This is a FORTRAN IV program which allows the user to directly input boolean equations, from which it creates the fuse map which the programmer can understand. PALASM, being a product of MMI, only supports PALs.

Recently Data I/O, who manufactures programmers, and Structured Design, have each released second-generation compilers for programmable devices. These compilers (ABEL and CUPL, respectively) support all manufacturer's devices and provide more sophisticated facilities than were available on the original PALASM. They have macro capability, can do logic minimization, can simulate the target device, automatically generate test vectors, and are even device-independent, up to a point. Device independence means the same equations can be re-compiled for a different device. For example a PAL can be used in place of an FPLA, as long as the target device has the capability required by the application.


I'll use the PAL structure in Figure 5 for an application example. Admittedly, the example is a bit simplistic, but it will demonstrate the basic sum-of-products principle.

The example circuit is shown in Figure 7. It is a 2 to 1 multiplexer with a strobe. The truth table and logic equation is shown in Figure 8. The A/B input selects the A input when high, and the B input when low. The S input forces the output low unless it is high. The circuit in Figure 7 uses three types of gates, a 7404, a 7408, and a 7432. It uses 1/6 of the '04, 3/4 of the '08, and 1/4 of the '32, for a total of 1 1/6 14 pin packages. A PAL as a replacement for this logic would typically be a 20 pin package, but could replace much more than just this simple multiplexer. Figure 9 is the PAL in Figure 5 which has been programmed to perform the multiplexer function of Figure 7.

This example demonstrates the concept of programmable logic, and suggests that much more complicated logic substitutions are possible. In fact, PLDs are available with up to 64 inputs and 32 outputs, with registers (flip-flops) and feedback terms, and in a variety of technologies. CMOS and ultraviolet light eraseable PLDs are just coming on the market in what was once a completely bipolar domain. The market for these devices is growing rapidly and they should soon be as familiar to everyone as EPROMS are now.


The Macintosh uses six HAL devices, of four different types. These types are 16L8, 16R8, 16R6, and 16R4.

The 16L8 is very similar to the example I've given, with 8 dedicated input pins, and 8 pins which are programmable as inputs or outputs. The part number, 16L8, means there are 16 possible inputs, 8 possible outputs, and the outputs are active low. The active low outputs can be programmed as active high using DeMorgan's Law, as I described above.

The 16R8 is identical to the 16L8, only there is a D-type flip-flop (register) at the output of each OR term. Figure 10 shows the structure of one registered output term. The 16R6 and 16R4 have 6 and 4 output registers respectively, with the remaining 2 and 4 terms direct combinatorial outputs like the 16L8.


A look at the functions that the Mac's HALs perform give a good feel for the type of applications where programmable logic is used. There are many instances of simple random-logic replacement, but there are also some clever applications that demonstrate the versatility of these devices.

The 6 HALs in the Mac have designators silk-screened on the PC board next to them. I'll refer to them by those names, although I can't figure out what they stand for.


BMU1 is a 16L8 device which performs the major address decoding functions. It has as inputs the higher order address lines A21, A22, and A23 from the processor, along with the overlay bit (for a description of the overlay bit, see the August issue). These bits are decoded to generate enable signals for the RAM, ROM, the IWM (disk controller) and the SCC serial chip.


LAG is a 16R8 device which performs the majority of the video control functions. It has as inputs most of the video address counter outputs, which are decoded to create output signals which load the video shift register, provide the CRT sweep circuitry with horizontal and vertical syncs, increment and reset the video address counters, and switch the RAM address multilplexers between CPU, video, and sound addresses.


BMU0 is a 16R4 device which generates RAM read and write signals from the RAM enable output of BMU1 and the processor R/W line. It is also used as a counter to create two video address lines (VA12 and VA13) because the video counter is only 12 bits wide (VA0-VA11). In addition, it also generates DTACK, the data transfer acknowledge handshake signal to the processor, and synchronizes the output of the video shift register with the master oscillator. This is a very good example of the many different types of functions that can be handled with a single programmable device.


TSM is a 16R4 device whose major function is control of the dynamic RAM. For inputs, it has the decoded RAM enable signal, along with the address and data strobes from the processor which signify whether the data transfer will be low byte, hi byte, or word. From these the RAS and CAS strobes are generated, and the row/column address multiplexer is controlled. Until there were PALs, this type of dynamic RAM control function required either about 10-20 discrete TTL packages, or a 40 pin LSI dynamic RAM controller which usually didn't do what you wanted anyway.


ASG is a 16R8 device which illustrates why PALs can be so valuable. It's primary purpose is to take the 6-bit disk speed value which is fetched at the end of every horizontal retrace period and convert it to a pulse-width modulated signal. Basically, it's a 6-bit counter. This leaves a couple of inputs and an output available, which are used to control the loading of the sound generator pulse-width modulator, which is a counter made up of TTL devices. If a discrete counter had been used for the disk PWM, another chip would have been required for the sound PWM load function. Using a PAL for a simple counter function in this instance saved a chip in the design.


This one is my favorite. The TSG is a 16R6 device which illustrates the power of programmable logic. It serves a couple of mundane functions concerning interrupts and the keyboard clock, but by far it's most interesting job is as a clock generator for the SCC serial chip.

The master oscillator frequency in the Macintosh is 15.667 MHz. This is divided by 2 in the TSG to get the 7.834 MHz processor clock. In order for the SCC to be able to operate at a baud rate of 230.4 KBaud, which is what AppleTalk requires, it needs an input clock frequency of 3.686 MHz.

If you pull down your calculator desk accessory, you'll find that 15.667 ÷ 3.686 = 4.25. This means that the TSG needs to divide the 15.667 MHz master oscillator by 4.25 in order to get a 3.686 MHz clock. How is this done, since 4.25 is not even an integer, let alone a binary number?

Let's call the 15.667 MHz clock the MO_clk and the 3.686 MHz clock the SCC_clk. For every 17 MO_clk periods there are 4 SCC_clk periods (17 ÷ 4 = 4.25). The way the TSG generates the SCC_clk is count to 4 three times and then count to 5 once (4 + 4 + 4 + 5 = 17). See Figure 11 for a graphical description. Try that using a single TTL counter chip!

In reference to my opening paragraph, I hope by now everyone realizes that PALs aren't black magic. In fact, I'd term them white magic, since they are used not for evil, but for good.


PAL® and HAL® are registered trademarks and PALASM™ is a trademark of Monolithic Memories Inc.

REFERENCES: Programmable Array Logic Handbook, Monolithic Memories Inc., Santa Clara, CA 1981.

Integrated Fuse Logic Data Manual, Signetics Corp., Sunnyvale, CA 1984.


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